International Transaction Journal of Engineering, Management, & Applied Sciences & Technologies


:: International Transaction Journal of Engineering, Management, & Applied Sciences & Technologies

ISSN 2228-9860
eISSN 1906-9642


Vol.12(1) (2021)

  • Design and Implementation of Optimized LDPC for SDR Applications

    D. Sahaya Lenin and Himanshu Shekhar (Department of Electronics and Communication Engineering, Hindustan Institute of Technology and Science, Chennai, INDIA).

    Disciplinary: Electronics and Communication Engineering.

    ➤ FullText

    doi: 10.14456/ITJEMAST.2021.15

    Keywords: Software-defined radio (SDR); LDPC Decoding; LDPC structure encoding; SDR architectures; Parity generation; optimized LDPC.

    LDPC is a promising error correction protocol, which is widely useful for low-end wireless protocol standards. This lightweight protocol mechanism is suitable for basic SDR applications. The same is not true for high-end wireless communication due to its limitations. Since technological scaling on its own is insufficient to satisfy today's SDR architectures with these wireless standards. Hence by reducing the decoding complexity and by increasing capacity performance. We use this Low-Density Parity-Check codes in SDR based wireless communication platform. The major limitation of conventional LDPC code is high latency and power consumption with top design complexity. To overcome such a problem, the optimized LDPC encoding and decoding are proposed with less lag and power consumption without degrading the performance of the conventional design. The proposed model offers less hardware complexity used in telecommunication applications. This methodology is implemented and synthesized using Xilinx ISE tool.

    Paper ID: 12A1O

    Cite this article:

    Lenin, D. S., and Shekhar, H. (2021). Design and Implementation of Optimized LDPC for SDR Applications. International Transaction Journal of Engineering, Management, & Applied Sciences & Technologies, 12(1), 12A1O, 1-10.


  1. Chu, T., Jiang, X.Q., Hou, J., Hui-Ming, W., Kong L. Construction of multiple-rate LDPC codes using modified PEG. In 9th International Conference on Wireless Communications and Signal Processing (WCSP), 2017(1-5). IEEE.
  2. Chung, C.C., Sheng, D. and Ho, W.D., A low-cost low-power all-digital spread-spectrum clock generator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(5), 983-987, 2014.
  3. Darabiha A, Carusone AC, Kschischang FR. Power reduction techniques for LDPC decoders. IEEE Journal of Solid-State Circuits. 2008, 43(8): 1835-45.
  4. Deng L, Wang Y, Noor-A-Rahim MD, Guan YL, Shi Z, Gunawan E, Poh CL. Optimized code design for constrained DNA data storage with asymmetric errors. IEEE Access. 2019, 7, 84107-21.
  5. Fang Y, Han G, Chen P, Zhao L, Kong L. Protograph LDPC codes for STBC Rayleigh fading channels. In 15th International Symposium on Communications and Information Technologies, 2015 (93-96). IEEE.
  6. Honda J, Yamamoto H. Variable length lossy coding using an LDPC code. IEEE Transactions on Information Theory. 2013, 60(1):762-75.
  7. Lin S, Abdel-Ghaffar K, Li J, Liu K. A Novel Coding Scheme for Encoding and Iterative Soft-Decision Decoding of Binary BCH Codes of Prime Lengths. In2018 Information Theory and Applications Workshop (ITA) 2018 (1-10), IEEE.
  8. Park JY, Chung KS. An adaptive low-power LDPC decoder using SNR estimation. EURASIP Journal on Wireless Communications and Networking. 2011, 48.
  9. Pourjabar S, Choi GS. CVR: A Continuously Variable Rate LDPC Decoder Using Parity Check Extension for Minimum Latency. arXiv preprint arXiv:1904.12016. 2019.
  10. Qahtani, A.M., Low Power DSP Architecture For OFDM. InternationFal Journal of MC Square Scientific Research, 11(3), 17-22, 2019.
  11. Rajasekar B, Logashanmugam E. Modified greedy permutation algorithm for low complexity encoding in LDPC codes. In 2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 2014 (336-339). IEEE.
  12. V.Hanumanth Goud And Maria Jossy, Low Power Data Encoding Schemes in LDPC Applications. International Journal of Science, Engineering Research, 4(4), 2015, 1168-1172.
  13. Vijayalakshmi S, Nagarajan V. Energy efficient low-density parity check scheme for body channel communication using FPGA. Microprocessors and Microsystems. 2019, 68, 84-91.
  14. Wang G, Wu M, Yin B, Cavallaro JR. High throughput low latency LDPC decoding on GPU for SDR systems. In 2013 IEEE Global Conference on Signal and Information Processing 2013, 3 (pp. 1258-1261), IEEE.
  15. Wyglinski, A.M., Getz, R., Collins, T. and Pu, D., Software-defined radio for engineers. Artech House. 2018.
  16. Yin J, Li L, Zhang H, Li X, Gao A, Chen W, Han Z. High Throughput Parallel Concatenated Encoding and Decoding for Polar Codes: Design, Implementation and Performance Analysis. In 14th International Wireless Communications & Mobile Computing Conference (IWCMC), 2018 (pp. 1373-1378). IEEE.

Other issues:


Call-for-Scientific Papers
Call-for-Research Papers:
ITJEMAST invites you to submit high quality papers for full peer-review and possible publication in areas pertaining engineering, science, management and technology, especially interdisciplinary/cross-disciplinary/multidisciplinary subjects.

To publish your work in the next available issue, your manuscripts together with copyright transfer document signed by all authors can be submitted via email to Editor @ (no space between). (please see all detail from Instructions for Authors)

Publication and peer-reviewed process:
After the peer-review process (4-10 weeks), articles will be on-line published in the available next issue. However, the International Transaction Journal of Engineering, Management, & Applied Sciences & Technologies cannot guarantee the exact publication time as the process may take longer time, subject to peer-review approval and adjustment of the submitted articles.